As the device densities of integrated circuits continue to increase the metallurgy technologies utilized to interconnect individual devices must meet more stringent requirements. For one, higher device counts necessitate multiple levels of metal. As the number of metal levels increases, it is important that the insulator layer separating these metal layers be as planar as possible. If planarity is not maintained, the resulting severe topologies may cause metal opens or shorts. As a result a method to create a planar layer is currently desirable.
Another application where planarization is required is in trench isolated semiconductor devices. Trench isolation is a way of providing interdevice isolation. Trench isolation is applicable to both bipolar and field effect transistor technologies. Traditionally, trench isolation involves etching a narrow, deep trench or groove in a silicon substrate and then filling the trench with a filler material. Trenches are also often used in memory design to provide information storage capacity which requires good electrical connection to selected transistors. Existing trench isolation techniques, however, do not permit wide variations in the dimensions of the trench. For example, if a wafer contains both large and small trenches and the material is deposited so that it fills the trenches, the large trenches will not be completely filled. Furthermore, trenches formed by traditional techniques have upper surfaces which are difficult to planarize. Consequently, most designers who employ trenches are forced to use them in narrow interdevice regions and use conventional thermally grown field oxides in the wider interdevice regions.
A common insulating material used between metal levels, to fill isolation trenches, and as a conformal layer, is borophosphosilicate glass (BPSG). The BPSG layer is typically deposited conformally and therefore maintains the topography of the underling substrate. The glass layer can then be reflowed to create a more planar level or layer. The prior art reflow methods, however, do not create levels as planar as desired.
Another problem exists with the high temperatures which are required to reflow the glass layers. Typically temperatures of 900 degrees C or more are necessary. These high temperatures cause degradation of the underlying semiconductor device due to migration of dopant materials. In addition, the reflow temperatures are higher than those applicable to the commonly used aluminum. If the temperatures are lowered it is very difficult to reflow the BPSG over severe topographies.
Other known techniques, such as the planarization from spin-on glass and resist etchback, are not desirable from a reliability standpoint. This is because an active gas may remain in the glass layer creating chemical and physical instability in the film.
Accordingly, improvements which overcome any or all of the problems are presently desirable.